1. Technical Field
The present invention relates generally to a semiconductor memory device, and more particularly, to technology for performing a data erase operation.
2. Related Art
A known nonvolatile memory device such as a flash memory device includes a nonvolatile memory cell array comprising a plurality of nonvolatile memory cells. Each nonvolatile memory cell includes a transistor having a control gate and a floating gate.
Each of the nonvolatile memory cells may be a single-level cell (SLC) for storing one bit of data per cell. In other words, the single level cell (SLC) has two threshold voltage distributions. Furthermore, each of the nonvolatile memory cells may be a multi-level cell (MLC) for storing multiple bits of data per cell. In other words, the multi-level cell (MLC) can have three or more threshold voltage distributions (e.g., four threshold voltage distributions, eight threshold voltage distributions, etc.). Here, a threshold voltage distribution having the lowest level corresponds to an erased state. Here, the threshold voltage distribution has a Gaussian distribution shape.
If the threshold voltage distribution of the erased state is too wide because threshold voltages of some memory cells are too low, a large number of programming voltage pulses may need to be applied so as to program the memory cells having too low threshold voltages. Therefore, after an erase operation, a soft programming operation may be performed to form a threshold voltage distribution having a desired voltage level and shape.
In order to perform a soft programming operation, soft programming voltages are applied to word lines coupled to gates of the memory cells while applying ground voltages to channels of the memory cells. According to a known art, the ground voltage applied to the channel of the memory cell is supplied by a page buffer. The page buffer transmits the ground voltage to the channel of the memory cell through the bit line. Therefore, a time at which the ground voltage is supplied to the channel of the memory cell is delayed by a large loading value of the bit line. Furthermore, in order for the page buffer to provide the ground voltage, a large number of control signals should be used to control the page buffer.